品牌:1012222072 | 型号:NT5TU64M16GG | 类型:驱动IC |
驱动芯片类型:Q | 针脚数:8 | 用途:电视机 |
封装:BGA | 功率:220W | 批号:14 |
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG 1Gb DDR2 SDRAM 1 REV 1.0 CONSUMER DRAM Dec / 2009 漏 NANYA TECHNOLOGY CORP. All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. Feature CAS Latency Frequency Speed Bins -3C/-3CI (DDR2-667-CL5) -AC/-ACI (DDR2-800-CL5) -BD (DDR2-1066-CL6) Units Parameter min max min max min max tCK(Avg.) Clock Frequency 125 333 125 400 125 533 MHz tRCD 15 - 12.5 - 11.25 - ns tRP 15 - 12.5 - 11.25 - ns tRC 60 - 57.5 - 56.25 - ns tRAS 45 70K 45 70K 45 70K ns tCK(Avg.)@CL3 5 8 5 8 5 8 ns tCK(Avg.)@CL4 3.75 8 3.75 8 3.75 8 ns tCK(Avg.)@CL5 3 8 2.5 8 2.5 8 ns tCK(Avg.)@CL6 - - - - 1.875 8 ns tCK(Avg.)@CL7 - - - - 1.875 8 ns 飦 1.8V 卤 0.1V Power Supply Voltage 飦 8 internal memory banks 飦 Programmable CAS Latency: 3, 4, 5 (DDR2--3C/-AC) 6 (-BD) 飦 Programmable Additive Latency: 0, 1, 2, 3, 4 5 飦 Write Latency = Read Latency -1 飦 Programmable Burst Length: 飦 4 and 8 Programmable Sequential / Interleave Burst 飦 OCD (Off-Chip Driver Impedance Adjustment) 飦 ODT (On-Die Termination) 飦 4 bit prefetch architecture 飦 Data-Strobes: Bidirectional, Differential 飦 Support Industrial grade temperature -40鈩儈95鈩 Operating t Temperature (-3CI/-ACI) 飦 1KB page size for x4 and x8 2KB page size for x16 飦 Strong and Weak Strength Data-Output Driver 飦 Auto-Refresh and Self-Refresh 飦 Power Saving Power-Down modes 飦 7.8 碌s max. Average Periodic Refresh Interval 飦 RoHS Compliance 飦 Packages: 飦 60-Ball BGA for x4 / x8 components 飦 84-Ball BGA for x16 components NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG 1Gb DDR2 SDRAM 2 REV 1.0 CONSUMER DRAM Dec / 2009 漏 NANYA TECHNOLOGY CORP. All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. Description The 1giga bit (1Gb) Double-Data-Rate-2 (DDR2) DRAMs is a high-speed CMOS Double Data Rate 2 SDRAM containing 1,073,741,824 bits. It is internally configured as an octal-bank DRAM. The 1Gb chip is organized as 32Mbit x 4 I/O x 8 bank, 16Mbit x 8 I/O x 8 bank or 8Mbit x 16 I/O x 8 bank device. These synchronous devices achieve high speed double-data-rate transfer rates of up to 800 Mb/sec/pin for general appli-cations. The chip is designed to comply with all key DDR2 DRAM key features: (1) posted CAS with additive latency, (2) write latency = read latency -1, (3) normal and weak strength data-output driver, (4) variable data-output impedance adjustment and (5) an ODT (On-Die Termination) function. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and 飦冿亱 falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion. A 14 bit address bus for x4/x8 organized components and A 13 bit address bus for x16 component is used to convey row, column, and bank address devices. These devices operate with a single 1.8V 卤 0.1V power supply and are available in BGA packages