H9TQ26ABJTMCUR_KUM EMMC+LPDDR3 现货库存热卖中详细介绍

16GB eNAND (x8) / LPDDR3 16Gb(x32)

FEATURES

[ CI-MCP ]

鈼廜peration Temperature - (-25)oC ~ 85oC鈼廝ackage

 - 221-ball FBGA - 11.5x13.0mm2, 1.0t, 0.5mm pitch - Lead & Halogen Free[ e-NAND ]

    鈥� eMMC5.0 compatible                                                                (Backward compatible to eMMC4.5)   鈥� Bus mode

    - Data bus width : 1 bit(default), 4 bits, 8 bits    - Data transfer rate: up to 400MB/s (HS400)    - MMC I/F Clock frequency : 0~200MHz     - MMC I/F Boot frequency : 0~52MHz  鈥� Operating voltage range    - Vcc (NAND) : 2.7 - 3.6V 

    - Vccq (Controller) : 1.7 - 1.95V / 2.7 - 3.6V  鈥� Temperature 

   - Operation (-25鈩�   ~ +85鈩�)

   - Storage without operation (-40鈩�   ~ +85鈩�)  鈥� Others 

   - This product is compliance with the RoHS directive

   鈥� Supported features   - HS400, HS200  

   - HPI, BKOPS

   - Packed CMD, Cache   - Partitioning, RPMB

   - Discard, Trim, Erase, Sanitize   - Write protect, Lock / Unlock   - PON, Sleep / Awake   - Reliable write

   - Boot feature, Boot partition   - HW / SW Reset

   - Field firmware update

   - Configurable driver strength   - Health(Smart) report

   - Production state awareness   - Secure removal type

 [ LPDDR3 ]

飩� VDD1 = 1.8V (1.7V to 1.95V)飩� VDD2, VDDCA and VDDQ = 1.2V (1.14V to 1.30)飩� HSUL_12 interface (High Speed Unterminated Logic 1.2V)飩� Double data rate architecture for command, address and 

data Bus; 

- all control and address except CS_n, CKE latched at both rising and falling edge of the clock 

- CS_n, CKE latched at rising edge of the clock- two data accesses per clock cycle

飩� Differential clock inputs (CK_t, CK_c)

飩� Bi-directional differential data strobe (DQS_t, DQS_c)

- Source synchronous data transaction aligned to bi-direc-tional differential data strobe (DQS_t, DQS_c)- Data outputs aligned to the edge of the data strobe (DQS_t, DQS_c) when READ operation

- Data inputs aligned to the center of the data strobe (DQS_t, DQS_c) when WRITE operation

飩� DM masks write data at the both rising and falling edge of 

the data strobe

飩� Programmable RL (Read Latency) and WL (Write Latency) 飩� Programmable burst length: 8 飩� Auto refresh and self refresh supported

飩� All bank auto refresh and per bank auto refresh supported飩� Auto TCSR (Temperature Compensated Self Refresh)飩� PASR (Partial Array Self Refresh) by Bank Mask and Segment 

Mask

飩� DS (Drive Strength)飩� DPD (Deep Power Down)飩� ZQ (Calibration)

飩� ODT (On Die Termination