M12L2561616A-6TG2S 代理商原装***详细介绍

M12L2561616A-6TG2S

M14D1G1664A-2.5BG2S

y JEDEC standard 3.3V power supply y LVTTL compatible with multiplexed address y Four banks operation y MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ) y All inputs are sampled at the positive going edge of the system clock y Burst Read single write operation y DQM for masking y Auto & self refresh y 64ms refresh period (8K cycle) y All Pb-free products are RoHS-Compliant ORDERING INFORMATION Product ID Max Freq. Package Comments M12L2561616A-5TG2S 200MHz TSOP II Pb-free M12L2561616A-6TG2S 166MHz TSOP II Pb-free M12L2561616A-7TG2S 143MHz TSOP II Pb-free M12L2561616A-5BG2S 200MHz BGA Pb-free M12L2561616A-6BG2S 166MHz BGA Pb-free M12L2561616A-7BG2S 143MHz BGA Pb-free GENERAL DESCRIPTION The M12L2561616A is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 16 bits. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. PIN CONFIGURATION (TOP VIEW) BALL CONFIGURATION (TOP VIEW) (TSOPII 54L, 400milX875mil Body, 0.8mm Pin Pitch) (BGA54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS VSS DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 NC UDQM CLK A12 A11 A8 A7 VSS A5 VDDQ DQ0 VSSQ DQ2 VDDQ DQ4 VDD LDQM CAS RAS BA0 BA1 A0 A1 A3 A2 123456789 A B C D E F G H J VSSQ VDDQ VSSQ VDDQ VSS CKE A9 A6 A4 VDD DQ1 DQ3 DQ7 WE CS A10 VDD VSSQ DQ6 DQ5 ESMT M12L2561616A (2S) Elite Semiconductor Memory Technology Inc. Publication Date: Feb. 2015 Revision: 1.4 2/45 BLOCK DIAGRAM PIN DESCRIPTION PIN NAME INPUT FUNCTION CLK System Clock Active on the positive going edge to sample all inputs CS Chip Select Disables or enables device operation by masking or enabling all inputs except CLK , CKE and L(U)DQM CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior new command. Disable input buffers for power down in standby. A0 ~ A12 Address Row / column address are multiplexed on the same pins. Row address : RA0~RA12, column address : CA0~CA8 BA1, BA0 Bank Select Address Selects bank to be activated during row address latch time. Selects bank for read / write during column address latch time. RAS Row Address Strobe Latches row addresses on the positive going edge of the CLK with RAS low. (Enables row access & precharge.) CAS Column Address Strobe Latches column address on the positive going edge of the CLK with CAS low. (Enables column access.) WE Write Enable Enables write operation and row precharge. Latches data in starting from CAS , WE active. L(U)DQM Data Input / Output Mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active. DQ0 ~ DQ15 Data Input / Output Data inputs / outputs are multiplexed on the same pins. VDD / VSS Power Supply / Ground Power and ground for the input buffers and the core logic. VDDQ / VSSQ Data Output Power / Ground Isolated power supply and ground for the output buffers to provide improved noise immunity. NC No Connection This pin is recommended to be left No Connection on the device.